About the Inventor

中村 維男(なかむら ただお)

Tadao Nakamura

Tadao Nakamura was born in Yamaguchi prefecture in 1944. He received his PhD from Tohoku University in 1972. He was a Full Professor at Tohoku University from 1988-2007, and successively became a Professor Emeritus of this university. In parallel he has been a Professor at Stanford University as visiting status. In 2007 he was inducted as a Professorial Fellow at Imperial College London (The University of London), and also became a Professor of Keio University. So far he lectured at University of Tokyo, University of Cambridge, etc. In addition, he is the CTO of Tops Systems and especially currently is a Senior Advisor of Dimarcia.

At Stanford University, Dr. Nakamura, with Professor Michael J. Flynn, invented “Marching Memory MM” which realizes memory access speed 1000 times faster than conventional DRAM’s, with other outstanding features such as large memory capacity size and lower energy consumption. As a result, they have created a novel ultra-high speed computer architecture without the memory bottleneck using MMs. This architecture enables the software to be unchanged and hardware to be quite simple. So totally the computer is lower energy consumed and low cost with simple fabrication and building up under the conventional fabrication technology and equipment.

He received Taylor L. Booth Award from the IEEE Computer Society in 2004. This award is given to just one person per year and he is the second professor at Stanford University to win this award. After he served as Organizing Committee Chair of the COOL Chips in IEEE Symposium, he has been its Advisory Committee Chair. He is Life Fellow of the IEEE.